SPICE2/3 Legacy Models

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SPICE2/3 Legacy Models

This section describes the basic SPICE2/3 models. The level 1-3 and 6 models can be used for quick analysis and examples, but are probably not suitable for serious design work using modern deep-submicron devices. The BSIM1 and BSIM2 models are for compatibility only, and are not likely to be useful except for analysis of legacy projects.

The dc characteristics of the level 1 through level 3 MOSFETs are defined by the device parameters vto, kp, lambda, phi and gamma. These parameters are computed by WRspice if process parameters (nsub, tox, ...) are given, but user-specified values always override. The parameter vto is positive (negative) for enhancement mode and negative (positive) for depletion mode N-channel (P-channel) devices. Charge storage is modeled by three constant capacitors, cgso, cgdo, and cgbo which represent overlap capacitances, by the nonlinear thin-oxide capacitance which is distributed among the gate, source, drain, and bulk regions, and by the nonlinear depletion-layer capacitances for both substrate junctions divided into bottom and periphery, which vary as the mj and mjsw power of junction voltage respectively, and are determined by the parameters cbd, cbs, cj, cjsw, mj, mjsw and pb. Charge storage effects are modeled by the piecewise linear voltage dependent capacitance model proposed by Meyer. The thin-oxide charge storage effects are treated slightly differently for the level 1 model. These voltage-dependent capacitances are included only if tox is specified in the input description and they are represented using Meyer's formulation.

There is some overlap among the parameters describing the junctions, e.g., the reverse current can be input either as is (in Amps) or as js (in Amps/m² ). Whereas the first is an absolute value, the second is multiplied by ad and as to give the reverse current of the drain and source junctions respectively. This methodology has been chosen to avoid always relating junction characteristics with ad and as entered on the device line; the areas can be defaulted. The same idea applies also to the zero-bias junction capacitances cbd and cbs (in Farads) on one hand, and cj (in F/m² ) on the other. The parasitic drain and source series resistance can be expressed as either rd and rs (in ohms) or rsh (in ohms/sq.), the latter being multiplied by the number of squares nrd and nrs input on the device line.

MOS Level 1 to Level 3 Parameters

name parameter units default example

level Model index - 1

vto zero-bias threshold voltage V 0.0 1.0

kp transconductance parameter A/V² 2.0e-5 3.1e-5

gamma bulk threshold parameter V^1/2 0.0 0.37

phi surface potential V 0.6 0.65

lambda channel-length modulation (MOS1 and MOS2 only) 1/V 0.0 0.02

rd drain ohmic resistance $\Omega$ 0.0 1.0

rs source ohmic resistance $\Omega$ 0.0 1.0

cbd zero-bias B-D junction capacitance F 0.0 20fF

cbs zero-bias B-S junction capacitance F 0.0 20fF

is bulk junction saturation current A 1.0e-14 1.0e-15

pb bulk junction potential A 0.8 0.87

cgso gate-source overlap capacitance per channel width F/M 0.0 4.0e-11

cgdo gate-drain overlap capacitance per channel width F/M 0.0 4.0e-11

cgbo gate-bulk overlap capacitance per channel length F/M 0.0 2.0e-10

rsh drain and source diffusion sheet resistance $\Omega$ / $\Box$ 0.0 10.0

cj zero-bias bulk junction bottom capacitance per junction area F/M² 0.0 2.0e-4

mj bulk junction bottom grading coeff - 0.5 0.5

cjsw zero-bias bulk junction sidewall capacitance per junction perimeter F/M 0.0 1.0e-9

mjsw bulk junction sidewall grading coeff. - 0.50 (level 1),
0.33 (level 2,3) -

js bulk junction saturation current per junction area A/M² 1.0e-8 -

tox oxide thickness M 1.0e-7 1.0e-7

nsub substrate doping 1/cM³ 0.0 4.0e15

nss surface state density 1/cM² 0.0 1.0e10

nfs fast surface state density 1/cM² 0.0 1.0e10

tpg type of gate material: +1 opp. to substrate, -1 same as substrate, 0 Al gate - 1.0 -

xj metallurgical junction depth M 0.0 1u

ld lateral diffusion M 0.0 0.8u

uo surface mobility cM²/VS 600 700

ucrit critical field for mobility degradation (MOS2 only) V/cM 1.0e4 1.0e4

uexp critical field exponent in mobility degradation (MOS2 only) - 0.0 0.1

utra transverse field coeff (mobility) (deleted for MOS2) - 0.0 0.3

vmax maximum drift velocity of carriers M/S 0.0 5.0e4

neff total channel charge (fixed and mobile) coefficient (MOS2 only) - 1.0 5.0

kf flicker noise coefficient - 0.0 1.0e-26

af flicker noise exponent - 1.0 1.2

fc coefficient for forward-bias depletion capacitance formula - 0.5 -

delta width effect on threshold voltage (MOS2 and MOS3) - 0.0 1.0

theta mobility modulation (MOS3 only) 1/V 0.0 0.1

eta static feedback (MOS3 only) - 0.0 1.0

kappa saturation field factor (MOS3 only) - 0.2 0.5

tnom parameter measurement temperature C 25 50

MOS Level 1 to Level 3 Parameters
name	parameter	units	default	example
`level`	Model index	-	1
`vto`	zero-bias threshold voltage	V	0.0	1.0
`kp`	transconductance parameter	A/V²	2.0e-5	3.1e-5
`gamma`	bulk threshold parameter	V^1/2	0.0	0.37
`phi`	surface potential	V	0.6	0.65
`lambda`	channel-length modulation (MOS1 and MOS2 only)	1/V	0.0	0.02
`rd`	drain ohmic resistance	$\Omega$	0.0	1.0
`rs`	source ohmic resistance	$\Omega$	0.0	1.0
`cbd`	zero-bias B-D junction capacitance	F	0.0	20fF
`cbs`	zero-bias B-S junction capacitance	F	0.0	20fF
`is`	bulk junction saturation current	A	1.0e-14	1.0e-15
`pb`	bulk junction potential	A	0.8	0.87
`cgso`	gate-source overlap capacitance per channel width	F/M	0.0	4.0e-11
`cgdo`	gate-drain overlap capacitance per channel width	F/M	0.0	4.0e-11
`cgbo`	gate-bulk overlap capacitance per channel length	F/M	0.0	2.0e-10
`rsh`	drain and source diffusion sheet resistance	$\Omega$ / $\Box$	0.0	10.0
`cj`	zero-bias bulk junction bottom capacitance per junction area	F/M²	0.0	2.0e-4
`mj`	bulk junction bottom grading coeff	-	0.5	0.5
`cjsw`	zero-bias bulk junction sidewall capacitance per junction perimeter	F/M	0.0	1.0e-9
`mjsw`	bulk junction sidewall grading coeff.	-	0.50 (level 1), 0.33 (level 2,3)	-
`js`	bulk junction saturation current per junction area	A/M²	1.0e-8	-
`tox`	oxide thickness	M	1.0e-7	1.0e-7
`nsub`	substrate doping	1/cM³	0.0	4.0e15
`nss`	surface state density	1/cM²	0.0	1.0e10
`nfs`	fast surface state density	1/cM²	0.0	1.0e10
`tpg`	type of gate material: +1 opp. to substrate, -1 same as substrate, 0 Al gate	-	1.0	-
`xj`	metallurgical junction depth	M	0.0	1u
`ld`	lateral diffusion	M	0.0	0.8u
`uo`	surface mobility	cM²/VS	600	700
`ucrit`	critical field for mobility degradation (MOS2 only)	V/cM	1.0e4	1.0e4
`uexp`	critical field exponent in mobility degradation (MOS2 only)	-	0.0	0.1
`utra`	transverse field coeff (mobility) (deleted for MOS2)	-	0.0	0.3
`vmax`	maximum drift velocity of carriers	M/S	0.0	5.0e4
`neff`	total channel charge (fixed and mobile) coefficient (MOS2 only)	-	1.0	5.0
`kf`	flicker noise coefficient	-	0.0	1.0e-26
`af`	flicker noise exponent	-	1.0	1.2
`fc`	coefficient for forward-bias depletion capacitance formula	-	0.5	-
`delta`	width effect on threshold voltage (MOS2 and MOS3)	-	0.0	1.0
`theta`	mobility modulation (MOS3 only)	1/V	0.0	0.1
`eta`	static feedback (MOS3 only)	-	0.0	1.0
`kappa`	saturation field factor (MOS3 only)	-	0.2	0.5
`tnom`	parameter measurement temperature	C	25	50

The level 4 (BSIM1) parameters are all values obtained from process characterization, and can be generated automatically. J. Pierret[3] describes a means of generating a ``process'' file, and the program proc2mod provided with WRspice will convert this file into a sequence of .model lines suitable for inclusion in WRspice input. Parameters marked below with an * in the l/w column also have corresponding parameters with a length and width dependency. For example, vfb is the basic parameter with units of volts, and lvfb and wvfb also exist and have units of volt- $\mu$ meter. The formula

P = P₀ + $\displaystyle {\frac{{P_L}}{{L_{effective}}}}$ + $\displaystyle {\frac{{P_W}}{{W_{effective}}}}$

is used to evaluate the parameter for the actual device specified with

L_effective = L_input - dl

and

W_effective = W_input - dw.

Note that unlike the other models in WRspice, the BSIM model is designed for use with a process characterization system that provides all the parameters, thus there are no defaults for the parameters, and leaving one out is considered an error. For an example set of parameters and the format of a process file, see the SPICE2 implementation notes[2].

BSIM (Level 4) Parameters

name l/w parameter units

vfb * flat-band voltage V

phi * surface inversion potential V

k1 * body effect coefficient V^1/2

k2 * drain/source depletion charge sharing coefficient -

eta * zero-bias drain-induced barrier lowering coefficient -

muz zero-bias mobility cM²/VS

dl shortening of channel $\mu$ M

dw narrowing of channel $\mu$ M

u0 * zero-bias transverse-field mobility degradation coefficient V^-1

u1 * zero-bias velocity saturation coefficient $\mu$ M/V

x2mz * sens. of mobility to substrate bias at Vds = 0 cM²/V²S

x2e * sens. of drain-induced barrier lowering to substrate bias V^-1

x3e * sens. of drain-induced barrier lowering to drain bias at Vds = Vdd V^-1

x2u0 * sens. of transverse field mobility degradation to substrate bias V^-2

x2u1 * sens. of velocity saturation effect to substrate bias $\mu$ MV^-2

mus mobility at zero substrate bias and at Vds = Vdd cM²/V²S

x2ms * sens. of mobility to substrate bias at Vds = Vdd cM²/V²S

x3ms * sens. of mobility to drain bias at Vds = Vdd cM²/V²S

x3u1 * sens. of velocity saturation effect on drain bias at Vds = Vdd $\mu$ MV^-2

tox gate oxide thickness $\mu$ M

temp temperature at which parameters were measured C

vdd measurement bias range V

cgdo gate-drain overlap capacitance per channel width F/M

cgso gate-source overlap capacitance per channel width F/M

cgbo gate-bulk overlap capacitance per channel length F/M

xpart gate-oxide capacitance charge model flag -

n0 * zero-bias subthreshold slope coefficient -

nb * sens. of subthreshold slope to substrate bias -

nd * sens. of subthreshold slope to drain bias -

rsh drain and source diffusion sheet resistance $\Omega$ / $\Box$

js source drain junction current density A/M²

pb built in potential of source drain junction V

mj grading coefficient of source drain junction -

pbsw built in potential of source,drain junction sidewall V

mjsw grading coefficient of source drain junction sidewall -

cj source drain junction capacitance per unit area F/M²

cjsw source drain junction sidewall capacitance per unit length F/M

wdf source drain junction default width M

dell source drain junction length reduction M

BSIM (Level 4) Parameters
name	l/w	parameter	units
`vfb`	*	flat-band voltage	V
`phi`	*	surface inversion potential	V
`k1`	*	body effect coefficient	V^1/2
`k2`	*	drain/source depletion charge sharing coefficient	-
`eta`	*	zero-bias drain-induced barrier lowering coefficient	-
`muz`		zero-bias mobility	cM²/VS
`dl`		shortening of channel	$\mu$ M
`dw`		narrowing of channel	$\mu$ M
`u0`	*	zero-bias transverse-field mobility degradation coefficient	V^-1
`u1`	*	zero-bias velocity saturation coefficient	$\mu$ M/V
`x2mz`	*	sens. of mobility to substrate bias at Vds = 0	cM²/V²S
`x2e`	*	sens. of drain-induced barrier lowering to substrate bias	V^-1
`x3e`	*	sens. of drain-induced barrier lowering to drain bias at Vds = Vdd	V^-1
`x2u0`	*	sens. of transverse field mobility degradation to substrate bias	V^-2
`x2u1`	*	sens. of velocity saturation effect to substrate bias	$\mu$ MV^-2
`mus`		mobility at zero substrate bias and at Vds = Vdd	cM²/V²S
`x2ms`	*	sens. of mobility to substrate bias at Vds = Vdd	cM²/V²S
`x3ms`	*	sens. of mobility to drain bias at Vds = Vdd	cM²/V²S
`x3u1`	*	sens. of velocity saturation effect on drain bias at Vds = Vdd	$\mu$ MV^-2
`tox`		gate oxide thickness	$\mu$ M
`temp`		temperature at which parameters were measured	C
`vdd`		measurement bias range	V
`cgdo`		gate-drain overlap capacitance per channel width	F/M
`cgso`		gate-source overlap capacitance per channel width	F/M
`cgbo`		gate-bulk overlap capacitance per channel length	F/M
`xpart`		gate-oxide capacitance charge model flag	-
`n0`	*	zero-bias subthreshold slope coefficient	-
`nb`	*	sens. of subthreshold slope to substrate bias	-
`nd`	*	sens. of subthreshold slope to drain bias	-
`rsh`		drain and source diffusion sheet resistance	$\Omega$ / $\Box$
`js`		source drain junction current density	A/M²
`pb`		built in potential of source drain junction	V
`mj`		grading coefficient of source drain junction	-
`pbsw`		built in potential of source,drain junction sidewall	V
`mjsw`		grading coefficient of source drain junction sidewall	-
`cj`		source drain junction capacitance per unit area	F/M²
`cjsw`		source drain junction sidewall capacitance per unit length	F/M
`wdf`		source drain junction default width	M
`dell`		source drain junction length reduction	M

The parameter xpart = 0 selects a 40/60 drain/source charge partition in saturation, while xpart = 1 selects a 0/100 drain/source charge partition.

Next: Imported MOS Models Up: MOSFET Models (both N Previous: MOS Model Binning Contents Index

Stephen R. Whiteley 2024-10-26