Simulation Options

In any SPICE-like program, the .options line in input allows setting of variables and flags that control aspects of the simulation run. WRspice provides this support as well, however in a more general context as there is little difference between ``options'' and ``variables'', as set with the set command. In WRspice, an ``option'' is simply a variable set in the .options line of an input file that has been sourced.

The options are stored in a table within the circuit structure, and are in force when the circuit is the current circuit. In the listing or variables provided from the set command given with no arguments, or in the Variables tool from the Tools menu in the Tool Control window, the option variables that are in force are indicated with a `+' in the first column.

The variables set in the .options line may be available for substitution (into $variable references) when the circuit is the current circuit, but otherwise do not affect the shell. For example, setting the variable noglob from a .options line will not affect the global expansion of the shell, but references to $noglob would behave as if the boolean noglob was set, while the circuit is the current circuit.

Shell variables set in the .options line are set before the rest of the SPICE text is expanded, so that shell variable references in the text can be defined from the .options line, as in the .exec block. The .exec lines are executed before the .options lines are expanded.

Since options can be set in the shell, as well as from the circuit, WRspice must merge the two sets of variables according to some rule. The rule allows three variations:

1. global mode (the default)
   In global options merging, if a boolean variable is set in either the circuit or the shell, it is taken as set. If a non-boolean variable is set in only one of the circuit or the shell, the variable is taken as set using the given value. If a non-boolean variable is set in both the circuit and the shell, the shell value will be used.

   This is the default mode, and the only mode available in Berkeley SPICE3. This allows the interactive user to use the set command to override options set in the circuit file. This may also be somewhat dangerous, as the shell override may occur for a forgotten variable, causing the user to wonder about strange results.

2. local mode
   This is similar to global mode, except that in the case of a non-boolean variable being defined in both the circuit and the shell, the circuit definition will apply.

   In this mode, the set command can be used to set circuit variables that were not defined on .options lines in the circuit file. The set command will have no effect on variables that were defined in this way.

3. noshell mode
   In this mode, the circuit will ignore variables set in the shell, and apply only variables set in .options lines. This applies, however, only to the set of variables that affect circuit setup or simulation, as listed in the table below. It also only applies during the actual circuit setup and simulation runs. It does not apply when the shell is running commands, such as from .control and .exec lines, or other scripts. The mode is taken as local in these cases.

There are two variables which control the option merging mode. Both, like any variables, can be set from the shell or from the circuit via .options lines.

optmerge
This variable can be set to one of three string constants: ``global'', ``local'', or ``noshell''.

noshellopts
This boolean variable is deprecated. When set, it will override optmerge if also given, and force the ``noshell'' mode.

.

If set in both the shell and the circuit, resolution is according to these rules.

• If noshellopts is set in the circuit or from the shell, it will be in effect, setting noshell mode.

• Otherwise, if optmerge is set to ``noshell'' in either the circuit or the shell, noshell mode will be in effect.

• Otherwise, if optmerge is set to ``local'' in either the circuit or the shell, local mode will be in effect.

• Otherwise, the global mode is in effect.

The table below is a listing of the ``official'' options. What makes these variables official options is that most of these set a flag or value in the circuit data structure, which is used when simulations are run. This is in addition to the setting of the variable in the normal database for variables, which is used for shell variable substitution, etc. From the user's perspective, there is no real distinction between ``options'' and ``variables''. A complete description of each of these variables is provided in 4.10.4.

Parameter Name	Description
Real-Valued Parameters
abstol	The absolute current error tolerance of the program.
chgtol	The minimum charge used when computing the time step in transient analysis.
dcmu	Mixing parameter to help dc convergence.
defad	The default value for MOS drain diffusion area.
defas	The default value for MOS source diffusion area.
defl	The value for MOS channel length.
defw	The value for MOS channel width.
delmin	The minimum time step allowed.
dphimax	The maximum allowed phase change per time step.
jjdphimax	An alias for dphimax.
gmax	The maximum conductance allowed in circuit equations.
gmin	The minimum conductance allowed in circuit equations.
maxdata	Maximum output data size in kilobytes.
minbreak	The minimum time, in seconds, between breakpoints.
pivrel	The relative ratio between the largest column entry and an acceptable pivot value.
pivtol	The absolute minimum value for a matrix entry to be accepted as a pivot.
rampup	Time to ramp up sources in transient analysis.
reltol	The relative error tolerance of the program.
temp	The assumed circuit operating temperature.
tnom	The nominal temperature for device model parameters.
trapratio	The threshold for trapezoidal integration convergence failure detection.
trtol	The transient time step prediction factor, the approximate overestimation of the actual truncation error.
vntol	The absolute voltage error tolerance of the program.
xmu	The SPICE2 trapezoidal/Euler mixing parameter.
Read-Only Real-Valued Parameters
delta	Transient analysis internal time step.
fstart	AC analysis start frequency.
fstop	AC analysis end frequency.
maxdelta	Transient analysis maximum internal time step.
tstart	Transient analysis start output time.
tstep	Transient analysis print increment.
tstop	Transient analysis final time.
Integer-Valued Parameters
bypass	Set to 0 to disable element computation bypassing.
fpemode	Set floating point error handling method (0-3).
gminsteps	The number of increments to use for non-dynamic gmin stepping.
interplev	The interpolation level used for scale data.
itl1	The dc operating pointiteration limit.
itl2	The dc transfer curve iteration limit.
itl2gmin	The iteration limit that applies during gmin stepping.
itl2src	The iteration limit that applies during source stepping.
itl4	The transient timepoint iteration limit.
loadthrds	The number of helper threads used for device evaluation and matrix loading.
loopthrds	The number of helper threads used when performing repeated analysis.
maxord	The maximum integration order.
srcsteps	The number of increments to use for non-dynamic source stepping.
itl6	An alias for srcsteps.
vastep	Verilog time step mapping.
Boolean Parameters
dcoddstep	Always include range end point in dc sweep.
extprec	Use extended precision when solving circuit equations.
forcegmin	Enforce all nodes mave at least gmin conductivity to ground.
gminfirst	Attempt gmin stepping before source stepping.
hspice	Suppress warnings from unsupported HSPICE input.
jaccel	Attempt to speed up Josephson junction transient analysis.
noiter	Don't Newton iterate.
nojjtp	>Don't use Josephson junction time step limiting.
noklu	Don't use KLU sparse matrix solver, use SPICE3 Sparse.
nomatsort	With Sparse solver, don't sort elements for cache locality.
noopiter	Skip initial dc convergence attempt.
nopmdc	Do not allow phase-mode DC analysis.
noshellopts	Ignore circuit variables not set in .options line.
oldlimit	Use SPICE2 voltage limiting.
oldsteplim	Use SPICE3/WRspice-3 timestep limiting.
renumber	Renumber lines after subcircuit expansion.
savecurrent	Save device current special vectors.
spice3	Use the SPICE3 integration level control logic in transient analysis.
translate	Map node numbers into matrix assuming nodes are not compact.
trapcheck	Perform trapezoidal integration convergence testing in transient analysis.
trytocompact	Enable compaction in LTRA (lossy transmission line) model.
useadjoint	Create an adjoint matrix for BSIM device current monitoring.
vasilent	Suppress run time text output from Verilog-A device models.
String Parameters
method	Integration method: ``trap'' (default) or ``gear''.
optmerge	Options merging method: ``global'' (default) or ``local'' or ``noshell''.
parhier	Parameter substitution precedence: ``global'' (default) or ``local''.
steptype	Time advancement method: ``interpolate'' (default) or ``hitusertp'', ``nousertp'', ``fixedstep''.
tjm_path	Amplitude table file search path for Josephson junction model.
Batch and Output Parameters
acct	Print accounting information in batch output.
dev	Print device list in batch output.
list	Print a listing of the input file in batch output.
mod	Print device model list in batch output.
node	Print a tabulation of the operating point node voltages in batch output.
nopage	Suppress page breaks in batch output.
numdgt	Number of significant digets printed in output.
opts	Print a summary of the specified options in batch output.
post	Give post-simulation option.
Obsolete/Unsupported Parameters
cptime	Obsolete SPICE2 parameter.
itl3	Obsolete SPICE2 parameter.
itl5	Obsolete SPICE2 parameter.
limpts	Obsolete SPICE2 parameter.
limtim	Obsolete SPICE2 parameter.
lvlcod	Obsolete SPICE2 parameter.
lvltim	Obsolete SPICE2 parameter.
nomod	Obsolete SPICE2 parameter.