This assigns the text value to the text token name. The name must start with a letter or underscore. If the text string name, delimited by space or one of ,)(='" but not with `=' to the right is found in the text, it is replaced by its value.
In 4.1.12 and later, node names are not parameter expanded by default. The boolean variable pexnodes if set will enable parameter expansion of node names, for backward compatibility with files that may have used this feature. Also in 4.1.12, device and subcircuit instance names are not parameter expanded, nor or subcircuit and model names found in .subckt and .model lines.
The `%' concatenation character is recognized. The concatenation character is used to separate the token from the other text: for example RES%K allows RES to be identified as a token, and if RES is `1' the substitution would yield `1K'. The name token must be surrounded by non-alphanumeric characters.
The concatenation character can be set to a different character with the var_catchar variable. If this variable is set to a string consisting of a single punctuation character, then that character becomes the concatenation character.
Substitutions occur on a second pass, so the order of definition and reference is not important (except when used in .if or .elif, described below). Substitutions are not performed in Verilog blocks, but are performed everywhere else. The .param lines always have global scope, meaning that they apply to the entire circuit, whether or not they are located within .subckt blocks.
Values can contain parameter references, i.e., nesting is accepted.
It is also possible to define ``user defined'' functions using the second form above. This is similar to to the define shell function, but functions defined in this manner exist only transiently, and will override a function of the same name and argument count defined with the define command.