The ``models'' provided with foundry design kits (for example) have become quite complex, to the point where loading these files into WRspice can take appreciable time. These files often encapsulate device calls into subcuits, and use large numbers of parameter definitions that must be processed into internal tables.
This overhead is annoying when simulating circuits, but can become a real problem when doing repetitive simulations such as for Monte Carlo analysis or when under control of a looping script. The caching feature enables one to load these definitions once only, on the first pass. Subsequent runs will reuse the internal representations, which can avoid most of the overhead.
The ``.cache'' and ``.endcache'' SPICE file keywords are used to identify lines of an input deck which will be cached. This syntax is non-standard and available only in WRspice.
The name is any short alpha-numeric name token, used to identify the cache block created. The cached representation of the enclosed lines is saved in WRspice memory under this name.
Presently, there can be only one .cache block per circuit deck. The first time the name is seen, the enclosed lines are processed normally but internal representations are saved. Subsequently, the enclosed lines are skipped. The skipping occurs very early in the sourcing operation, before .include and similar lines are read. So, for the example, the access to some_big_library is skipped entirely in subsequent runs.
If a different SPICE input file is sourced, and this has a .cache block with the same name as the first, the cached parameters from the first file will be used in the second file. The internal representation of the cache block has no attachment to any particular input file.
The Lines of SPICE input... which can appear between .cache and .endcache can be, after .include/.lib expansion:
The block can contain any of the .include/.lib family of lines, but after these lines are expanded, the resulting text should contain only the forms listed above. Anything else that appears in the cache block will likely cause an error, as it will be ``missing''.
The parameters from .param lines saved in the cache will override parameters of the same name defined elsewhere in the circuit file.
The subcircuit/model cache can be manipulated with the WRspice cache command.