This section describes the basic SPICE2/3 models. The level 1-3 and 6 models can be used for quick analysis and examples, but are probably not suitable for serious design work using modern deep-submicron devices. The BSIM1 and BSIM2 models are for compatibility only, and are not likely to be useful except for analysis of legacy projects.

The dc characteristics of the level 1 through level 3 MOSFETs are
defined by the device parameters `vto`, `kp`, `lambda`,
`phi` and `gamma`. These parameters are computed by
* WRspice* if process parameters (

There is some overlap among the parameters describing the junctions,
e.g., the reverse current can be input either as `is` (in Amps) or
as `js` (in Amps/m^{2}
). Whereas the first is an absolute value,
the second is multiplied by `ad` and `as` to give the reverse
current of the drain and source junctions respectively. This
methodology has been chosen to avoid always relating junction
characteristics with `ad` and `as` entered on the device line;
the areas can be defaulted. The same idea applies also to the
zero-bias junction capacitances `cbd` and `cbs` (in Farads) on
one hand, and `cj` (in F/m^{2}
) on the other. The parasitic drain
and source series resistance can be expressed as either `rd` and
`rs` (in ohms) or `rsh` (in ohms/sq.), the latter being
multiplied by the number of squares `nrd` and `nrs` input on
the device line.

MOS Level 1 to Level 3 ParametersnameparameterunitsdefaultexamplelevelModel index - 1 vtozero-bias threshold voltage V0.0 1.0 kptransconductance parameter A/V^{2}2.0e-5 3.1e-5 gammabulk threshold parameter V^{1/2}0.0 0.37 phisurface potential V0.6 0.65 lambdachannel-length modulation (MOS1 and MOS2 only) 1/ V0.0 0.02 rddrain ohmic resistance 0.0 1.0 rssource ohmic resistance 0.0 1.0 cbdzero-bias B-D junction capacitance F0.0 20fF cbszero-bias B-S junction capacitance F0.0 20fF isbulk junction saturation current A1.0e-14 1.0e-15 pbbulk junction potential A0.8 0.87 cgsogate-source overlap capacitance per channel width F/M0.0 4.0e-11 cgdogate-drain overlap capacitance per channel width F/M0.0 4.0e-11 cgbogate-bulk overlap capacitance per channel length F/M0.0 2.0e-10 rshdrain and source diffusion sheet resistance / 0.0 10.0 cjzero-bias bulk junction bottom capacitance per junction area F/M^{2}0.0 2.0e-4 mjbulk junction bottom grading coeff - 0.5 0.5 cjswzero-bias bulk junction sidewall capacitance per junction perimeter F/M0.0 1.0e-9 mjswbulk junction sidewall grading coeff. - 0.50 (level 1),

0.33 (level 2,3)- jsbulk junction saturation current per junction area A/M^{2}1.0e-8 - toxoxide thickness M1.0e-7 1.0e-7 nsubsubstrate doping 1/ cM^{3}0.0 4.0e15 nsssurface state density 1/ cM^{2}0.0 1.0e10 nfsfast surface state density 1/ cM^{2}0.0 1.0e10 tpgtype of gate material: +1 opp. to substrate, -1 same as substrate, 0 Al gate - 1.0 - xjmetallurgical junction depth M0.0 1u ldlateral diffusion M0.0 0.8u uosurface mobility cM^{2}/VS600 700 ucritcritical field for mobility degradation (MOS2 only) V/cM1.0e4 1.0e4 uexpcritical field exponent in mobility degradation (MOS2 only) - 0.0 0.1 utratransverse field coeff (mobility) (deleted for MOS2) - 0.0 0.3 vmaxmaximum drift velocity of carriers M/S0.0 5.0e4 nefftotal channel charge (fixed and mobile) coefficient (MOS2 only) - 1.0 5.0 kfflicker noise coefficient - 0.0 1.0e-26 afflicker noise exponent - 1.0 1.2 fccoefficient for forward-bias depletion capacitance formula - 0.5 - deltawidth effect on threshold voltage (MOS2 and MOS3) - 0.0 1.0 thetamobility modulation (MOS3 only) 1/ V0.0 0.1 etastatic feedback (MOS3 only) - 0.0 1.0 kappasaturation field factor (MOS3 only) - 0.2 0.5 tnomparameter measurement temperature C25 50

The level 4 (BSIM1) parameters are all values obtained from process
characterization, and can be generated automatically.
J. Pierret[3] describes a means of generating a ``process''
file, and the program `proc2mod` provided with * WRspice* will convert this
file into a sequence of

is used to evaluate the parameter for the actual device specified with

and

Note that unlike the other models in * WRspice*, the BSIM model is
designed for use with a process characterization system that provides
all the parameters, thus there are no defaults for the parameters, and
leaving one out is considered an error. For an example set of
parameters and the format of a process file, see the SPICE2
implementation notes[2].

BSIM (Level 4) Parametersnamel/wparameterunitsvfb* flat-band voltage Vphi* surface inversion potential Vk1* body effect coefficient V^{1/2}k2* drain/source depletion charge sharing coefficient - eta* zero-bias drain-induced barrier lowering coefficient - muzzero-bias mobility cM^{2}/VSdlshortening of channel Mdwnarrowing of channel Mu0* zero-bias transverse-field mobility degradation coefficient V^{-1}u1* zero-bias velocity saturation coefficient M/Vx2mz* sens. of mobility to substrate bias at Vds = 0 cM^{2}/V^{2}Sx2e* sens. of drain-induced barrier lowering to substrate bias V^{-1}x3e* sens. of drain-induced barrier lowering to drain bias at Vds = Vdd V^{-1}x2u0* sens. of transverse field mobility degradation to substrate bias V ^{-2}x2u1* sens. of velocity saturation effect to substrate bias MV^{-2}musmobility at zero substrate bias and at Vds = Vdd cM^{2}/V^{2}Sx2ms* sens. of mobility to substrate bias at Vds = Vdd cM^{2}/V^{2}Sx3ms* sens. of mobility to drain bias at Vds = Vdd cM^{2}/V^{2}Sx3u1* sens. of velocity saturation effect on drain bias at Vds = Vdd MV^{-2}toxgate oxide thickness Mtemptemperature at which parameters were measured Cvddmeasurement bias range Vcgdogate-drain overlap capacitance per channel width F/Mcgsogate-source overlap capacitance per channel width F/Mcgbogate-bulk overlap capacitance per channel length F/Mxpartgate-oxide capacitance charge model flag - n0* zero-bias subthreshold slope coefficient - nb* sens. of subthreshold slope to substrate bias - nd* sens. of subthreshold slope to drain bias - rshdrain and source diffusion sheet resistance / jssource drain junction current density A/M^{2}pbbuilt in potential of source drain junction Vmjgrading coefficient of source drain junction - pbswbuilt in potential of source,drain junction sidewall Vmjswgrading coefficient of source drain junction sidewall - cjsource drain junction capacitance per unit area F/M^{2}cjswsource drain junction sidewall capacitance per unit length F/Mwdfsource drain junction default width Mdellsource drain junction length reduction M

The parameter `xpart = 0` selects a 40/60 drain/source charge
partition in saturation, while `xpart = 1` selects a 0/100
drain/source charge partition.