Stage 1

1. Create a Cell Hierarchy Digest (CHD) in memory for the input file, if necessary.

2. Divide the area of the top-level cell into a logical grid.

3. For each grid area, the CHD is used to read into memory a flat representation of the grid area, clipped to the grid.

4. The wire nets for this area are identified. This can take into account device structures and exclusion areas.

5. An OASIS file is written to disk, which contains a subcell for each net found. Up to four edge-mapping files are also produced, one each for the edges that are shared with another grid cell. These files map the parts of the edge which coincide with the edge of a conducting object.

At the end of Stage 1, the work area on disk contains a number of OASIS files, one for each grid cell, and associated edge mapping files.

Note that the grid areas are processed sequentially. On a computer with limited memory, the grid size should be ``small'' so as to not exhaust available memory, but even a modest computer can process very large files. Note also that in theory this stage could easily be accelerated by use of multiple computers. Stage 1 is the most compute-intensive part of the flow.