In Virtuoso, foundry devices are most likely represented as parameterized cells (pcells). These are cells with an internal script which generates a physical layout according to a set of device parameters.
Parameterized cells in the Cadence environment are most probably based on the Skill language and are not portable outside of a Cadence environment. However, Virtuoso provides a feature called ``Express PCells'' which caches pcell sub-masters in the user's home directory. A pcell sub-master is an ordinary cell, created from a pcell using a specific parameter set. The pcell cache provides the benefit that pcell evaluation is avoided, so that designs may be opened more quickly. A second advantage is that the cached sub-masters, unlike the pcells, can be exported.
Before a design containing Skill-based pcell instances can be fully loaded into Xic, the Express PCell feature must be enabled, and all of the pcell submasters must be cached.
One should be aware that if only a schematic is being imported into Xic, it isn't necessary to worry about pcells, as the pcell schematic symbol is available. Only the physical layout changes with different device parameters.
To enable Express PCells, the environment variable CDS_ENABLE_EXP_PCELL should be set to ``true''. Again, this is most conveniently done in the user's shell startup script. For bash:
export CDS_ENABLE_EXP_PCELL=trueFor C-shell:
setenv CDS_ENABLE_EXP_PCELL true
From a Virtuoso Layout Editor window, the Tools menu will contain an Express PCell Manager button. This brings up a window allowing control of the feature. With the feature on, loading a design will populate the cache. It should then be possible to load the same design into Xic, with no unresolved pcell references. Note that when obtaining the pcell sub-masters through OpenAccess, a license checkout for the Cadence system occurs. Cadence will not export a sub-master from the cache without a license.