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Standard Vias

Xic provides a feature for creating and managing via objects used to connect between conducting layers in physical layouts. Although ordinary cells or cut-layer objects can be used for this purpose, use of standard vias offers some important advantages in many designs.

In order for this feature to be available, one or more standard vias definitions must appear in the technology file. These will also be imported from a Cadence Virtuoso ASCII technology file if the ReadCdsTech keyword is used, and the Cadence database contains standardViaDefs definitions. The implementation of standard vias in Xic closely follows the implementation in OpenAccess, and tools such as Virtuoso that use OpenAccess.

The standard vias that are defined in the technology provide the default definitions for a via structure. Although commonly instantiated directly, more commonly variations are implemented. There are a number of parameters that define the via, and these can be changed by the user to produce a variant most suitable in the context where it will be used. For example, the cut can be arrayed when lower contact resistance is required.

The mechanism is similar to a parameterized cell (pcell). The standard vias defined in the technology can be considered as the super-masters. When a via of a certain configuration is requested, a ``sub-master'' cell for that configuration is created in memory, if it hasn't been created previously. The instances of the via will reference that sub-master. Like pcells, the masters are not written to disk. Instead, when a file containing via placements is read, the via sub-masters are created in memory as needed.

An exception is when shipping a layout to another system, such as to a mask vendor. The Export Control panel from the Convert Menu is used for this purpose. If the Strip For Export check box is checked or equivalently if the StripForExport variable is set, which should be true in this situation, the via (and pcell) sub-masters are included in the layout file. The foreign system will see these as ordinary cells. The Include standard via cell sub-masters check box or equivalently the ViaKeepSubMasters variable will likewise cause inclusion of the via sub-masters in output when set.

A standard via definition provides values for a number of parameters. Of these, the numerical values can be changed by the user to form a variant. The layers involved are immutable. Each standard via definition has a unique name assigned in the technology. This name can be any text which is suitable as a cell name. One convention is to use the layer names of the two conductors, top layer first, separated by an underscore, e.g., ``M2_M1''. The parameters and their effects are described with the Via Creation panel, from which the parameters can be set, and variants created and placed.



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Next: The Standard Via Property Up: Parameterized Cells and Vias Previous: Importing a Design from   Contents   Index
Stephen R. Whiteley 2017-03-22