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- General Form:
.verilog
In WRspice, all Verilog code is placed into a block of statements
starting with a .verilog line and ending with a .endv
line. The Verilog block defines the modules of a hierarchy, including
a top-level ``stimulus'' module. The Verilog simulation is run in
parallel with transient analysis, where each user time increment
corresponds to one unit of Verilog time. The simulation is performed
as if steptype is set to hitusertp, i.e., simulation is
performed at each user time point. The Verilog simulation occurs
before the SPICE iterations at the time point. Signals are passed to
the Verilog block with .adc statements, and signals from the
Verilog block are accessed through referencing voltage or current
sources.
Output signals from the Verilog block are obtained through voltage or
current sources in the circuit. The voltage/current source must refer
by name to a Verilog variable in the scope of the top module, or use
the Verilog ``dot'' path notation. The voltage/current source is set
to the binary value of the variable, and has a built-in rise/fall time
of one time increment. The variable reference can contain a bit or
part select field.
A good primer on Verilog is: Samir Palnitkar, Verilog HDL, A
Guide to Digital Design and Synthesis, SunSoft Press (Prentice Hall)
ISBN 0-13-451675-3. The full story is in IEEE Standard 1364-1995.
An example input file that uses a .verilog block is given
in A.3.
Next: .adc Line
Up: Verilog Interface
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Stephen R. Whiteley
2006-10-23