|pijj=1|0||Whether the device is a ``pi'' junction.|
|area=val||Scale factor that multiplies all currents and other values, effectively modifying the junction area.|
|ics=val||Instantiated critical current, used as scale factor for capacitance, conductances.|
|lser=val||Junction series parasitic inductance.|
|lsh=val||Shunt resistor series parasitic inductance.|
|ic=vj,phi||The initial junction voltage and phase (initial condition) for transient analysis.|
|vj=vj||The initial junction voltage (initial condition) for transient analysis, alias ic_v.|
|phi=phi||The initial junction phase (initial condition) for transient analysis, alias ic_phase.|
|control=name||Controlling voltage source or inductor name.|
Unless stated otherwise, information presented here also applies to The Verilog-A Josephson junction model provided with WRspice in the Verilog-A examples.
The Josephson junction device has unique behavior which complicates simulation with a SPICE-type simulator. Central is the idea of phase, which is a quantum-mechanical concept and is generally invisible in the non-quantum world. However with superconductivity, and with Josephson junctions in particular, phase becomes not only observable, but a critical parameter describing these devices and the circuits that contain them.
Without going into the detailed physics, one can accept that phase is an angle which applies to any superconductor. The angle is a fixed value anywhere on the superconductor, unless current is flowing. Flowing current produces magnetic flux, and magnetic flux produces a change in phase. One can express this as follows:
LI = flux = (/2)
Here, L is the inductance, is the magnetic flux quantum (Planck's constant divided by twice the electron charge) and is the phase difference across the inductor. The supercurrent flowing in a Josephson junction is given by
I = Icsin()
where Ic is the junction critical current, and is the phase difference across the junction. The junction phase is proportional to the time integral of junction voltage:
The important consequence is that the sum of the phase differences around any loop consisting of Josephson junctions and inductors must be a multiple of 2 . This is due to the requirement that the superconducting wave function be continuous around the loop. Further, if the loop phase is not zero, it implies that a persistent current is flowing around the loop, and that the magnetic fluc through the loop is a multiple of the flux quantum .
We therefor observe that in a circuit containing loops of Josephson junctions and inductors, which includes about all useful circuits:
Without any built-in concept of phase, it would appear to be impossible to find the DC operating point of a circuit containing Josephson junctions and inductors with a SPICE simulator. However, there are ways to accomplish this.
The time-honored approach, used successfully for many years, is to skip DC analysis entirely. One generally is interested only in transient analysis, describing the time evolution of the circuit under stimulus, and a DC analysis would only be necessary to find the initial values of circuit voltages and currents. Instead of a DC analysis, what is done is every voltage and current source starts at zero voltage or current, and ramps to the final value in a few picoseconds. The transient analysis is performed using the ``use initial conditions'' (``uic'') option, where there is no DC operating point analysis, and transient analysis starts immediately with any supplied initial condicions (which are not generally given in this case). By ramping up from zero, the phase condition around junction/inductor loops is satisfied via Kirchhoff's voltage law. Actually, this ensures that the loop phase is constant, but it is zero as we started from zero. Initially, there is no ``trapped flux'' in the inductor/junction loops, so assumption of zero phase is correct. Thus the prescription is to ramp up all sources from zero, use the uic option of transient analysis, and wait for any transients caused by the ramping sources to die away before starting the ``real'' simulation. The ramping-up effectively replaces the DC operating point analysis.
WRspice after release 4.3.3 offers a DC analysis capability which uses phase-mode for circuits containing Josephson junctions. Unlike strictly phase-mode simulators, WRspice allows a mixture of phase (inductors and Josephson junctions) and voltage mode components.
Within WRspice, every node connected to a Josephson junction, inductor, or lossless transmission line (treated as an inductor in DC analysis) has a ``Phase'' flag set. This indicates that the computed value is phase, not voltage, for these nodes. We have to special-case the matrix loading functions for inductors, mutual inductors, lossless transmission lines, and resistors. Other devices are treated normally.
A Josephson junction can be modeled by the basic formula
I = Icsin(V(i, j))
where V(i, j) is the ``voltage'' difference between nodes i and j (across the junction) which is actually the phase. Inductors look like resistors:
I = V(i, j)/2L
Where V(i, j) is the phase difference across the inductor. Mutual inductance adds similar cross terms.
Capacitors are completely ignored as in normal DC analysis. The treatment of resistors is slightly complicated. The connected nodes can be ``Ground'', ``Phase'', or ``Voltage'' type. If both nodes are Voltage or Ground, the resistor is loaded normally. If both nodes are Phase or Ground, the resistor is not loaded at all. The interresting case is when one node is Phase, the other Voltage. In this case, we load the resistor as if the phase node is actually ground (node number 0). In addition we load a voltage-controlled current source template that injects current into the phase node of value V(voltage)/Resistance .
Resistors are the bridge between normal voltage-mode devices and phase nodes. Some circuits may require introduction of resistors to get correct results. For example, assume a Josephson junction logic gate driving a CMOS comparator circuit. If the input MOS gate is connected directly to the junction, the DC operating point will be incorrect, as the comparator will see phase as input. However, if a resistor separates the MOS gate from the junction, the comparator input will be zero, as it should be.
There is (at present) a topological requirement that all phase nodes must be at ground potential. This means that for a network of Josephson junctions and inductors, there must be a ground connection to one of these devices. A nonzero voltage source connected to an inductor, which is connected to a resistor to ground, although a perfectly valid circuit, will fail. One must use the equivalent consisting of the voltage source connected to a resistor, connected to the inductor which is grounded. This satisfies the two topological requirements:
With this bit of information, and the warning that controlled sources can cause unexpected behavior, the DC analysis using thes technique can apply to general circuits containing Josephson junctions.
Of course, for this to work, no Josephson junction can be biased above its critical current or nonconvergence results. Both DC operating point and DC sweep are available, as is AC analysis. Noise analysis is available with the internal Josephson junction model. This new hybrid technique appears to be an important advance, which should avoid the long-standing need to use ``uic'' and ramp sources up from zero, and makes available DC sweep analysis, and for the first time in any simulator AC small-signal analysis.
See the Josephson junction model description for more information.