How to Build a Module

If all goes according to plan, this is easy.

1. Create a fresh directory somewhere.

2. Copy the Makefile from the devkit directory (typically /usr/local/xictools/wrspice/devkit) into the new directory.

3. This is optional, but you may want to copy the Verilog-A source file (or files) into this directory as well, for convenience.

4. Edit the top of the Makefile with a text editor. The Makfile contains comments explaining what needs setting. Basically, you need to set the device key letter and model level (as will be used in WRspice), a short name for the module, and the path to the XML scripts provided under the devkit.

5. Type ``make'' at the shell prompt. The processing may take a few minutes. Some compiler warnings may appear.

   There may be a lot of messages like:

   warning: declaration of T10 shadows a previous local

   These appear when the module code defines a variable in a block, and also in a lower-level block. These should be harmless, but some models (bsimsoi) generate a lot of these messages.

   Messages like

   warning: unused variable vd

   appear if a variable is declared in a block but never used. Once again, these are harmless, but may represent declarations in the Verilog-A source that could be omitted.

6. If all goes well, a loadable module will be created. This is a file with a ``.so'' extension (``.dylib'' under OS X, or ``.dll'' in Windows) with the base name the same as the module name that was supplied in the Makefile. One should be able to load this module into WRspice, and access the device description in simulation files.