From the spec, this is not currently supported.
0 Prints nothing (the default if no argument) 1 Prints simulation time and location 2 Prints simulation time, location, and statistics about the memory and CPU time used in simulation
Verilog-AMS allows an additional option string argument to be specified to $finish to indicate the type of the finish. type_string can take one of three values: ``accepted'', ``immediate'' or ``current_analysis''. ``accepted is the default setting.
If the type_string is set to ``accepted'' and $finish is called during an accepted iteration, then the simulator will exit after the current solution is complete.
If the type_string is set to ``current_analysis'' and $finish is called during an accepted iteration, then the simulator terminates the current analysis and will start the next analysis if one requested.
If the type_string is set to ``immediate'' and $finish is called during an iteration, then the simulation will exit immediately without the current solution being completed. This is not recommended as it may leave the output files generated by the simulator in an undefined state.