The examples subdirectory contains several publicly-available Verilog-A models for testing and illustrating the procedure. The README files provide more information. You should copy the directories and their contents to your local directory to build the modules. In each model directory, follow the procedure above.
Test the new loadable module. First, verify that the loadable module file exists, i.e., the compile succeeded. Then, change to the ``tests'' subdirectory, and start WRspice. At the WRspice prompt, give the command
devload ../module.sowhere module.so is the actual name of the module file. WRspice will print a ``Loading device ...'' message, and no error messages should appear.
Next, bring up the File Selection panel with the File Select button in the File menu. There will be at least one file listed with a ``.sp'' or ``.cir'' extension, these are the SPICE input source files. Click on one of these to select, and click on the green octagon button. The simulation will run and a plot will appear.
Have fun!