Boolean Parameters

dcoddstep
Where set: Simulation Options/General

Consider the dc sweep specification

.dc vxxx 0 1.1 0.2

WRspice will evaluate at 0.0, 0.2, ... 1.0. If dcoddstep is given, evaluation will also be performed at the end-of-range value 1.1. This is the default for some other simulators, so dcoddstep provides compatibility.

extprec
Where set: Simulation Options/General

When this option is set, WRspice will use extended precision arithmetic when setting up and solving the circuit equations. With Intel, this mode uses the 80-bit native floating point format for all calculations, rather than the 64-bit ``double precision''. This requires that floating point numbers use 16 bytes rather than 8, however matrix space is allocated assuming complex numbers, which are 16 bytes. Thus, this mode has no memory-use penalty, and may actually cause some circuits to simulate faster.

The mode applies to both KLU and Sparse matrix solvers. It adds about three decimal digits of precision to the calculations. Using extended precision may avoid ``singular matrix'' and other convergence problems with some circuits. See and run the ``precision.cir'' file in the examples for more information.

forcegmin
Where set: Simulation Options/Convergence

When set, this will enforce a minimum gmin conductance to ground on all nodes in the circuit (including internal nodes of devices). This may facilitate convergence.

gminfirst
Where set: Simulation Options/Convergence

When this boolean option variable is set, during operating point analysis, gmin stepping is attempted before source stepping. This is the default in Berkeley SPICE, however the WRspice default is to apply source stepping first, which seems more effective.

hspice
Where set: Simulation Options/Parser

When set, many of the HSPICE parameters and keywords that are not handled are silently ignored. Ordinarily, these produce a warning message. In particular, when set:

1. The following MOS model parameters are silently ignored.

   acm alpha binflag calcacm capop cjgate cta

   ctp dtemp hdif iirat lalpha ldif lmlt

   lref lvcr mismatchflag nds pta ptp rd

   rdc rs rsc scale scalm sfvtflag sigma

   tlev tlevc vcr vnds walpha wmlt wref

   wvcr xl xw

2. The following BJT model parameters are silently ignored.

   iss

   ns

   tlev

   tlevc

   update

3. The following MOS device parameters are silently ignored.

   dtemp

4. The following control lines are silently ignored.

   .alias .alter .connect .data

   .dellib .dout .global .graph

   .hdl .lin .malias .protect

   .stim .unprotect

jjaccel
Where set: Simulation Options/Timestep

This applies only when Josephson junctions are present in the circuit, and performing transient analysis. It causes a faster convergence testing and iteration control algorithm to be used, rather than the standard more comprehensive algorithm suitable for all devices. If the circuit consists of Josephson junctions, passive elements, and sources only, then setting this option may provide a reduction in simulation time. It probably should not be used if semiconductor devices are present.

noiter
Not currently implemented.

During transient analysis, at each new time step, Newton iterations are used to solve the nonlinear circuit equations. The first iteration, the prediction step, uses extrapolation from past values to obtain a best guess at the solution for use as input. Additional iterations use the previous output values as input.

In cases where the nonlinearity is weak, or where the internal time step is forced to be small (as when Josephson junctions are present) iterations beyond the predictor sometimes lead to unneeded accuracy. Setting the variable noiter causes skipping of iterations beyond the prediction step, and also skipping of certain other code. This maximizes the simulation rate, but can lead to errors if not used carefully. Much the same effect can be obtained by setting reltol to a large value, however noiter is more efficient as convergence testing and matrix loading are skipped, as there is a-priori knowledge that no iterations are to take place. The iteration count and total internal timepoint count are available from the rusage command.

nojjtp
Where set: Simulation Options/Timestep

During transient analysis with Josephson junctions present, the default time step is given by T = $\phi$/vmax , where $\phi$ = $\Phi_{0}^{}$/2$\pi$ ($\phi$ = 3.291086546e-16, $\Phi_{0}^{}$ is the magnetic flux quantum) and vmax = max(Vj, sqrt($\phi$Jc/C)) . If the variable nojjtp is set, the timestep is determined from a truncation error calculation, as is the case when Josephson junctions are not present in the circuit. The user should experiment to determine which timestep leads to faster execution.

noklu
Where set: Simulation Options/General

When this boolean variable is set, KLU will not be used for sparse matrix calculations. Otherwise, if the KLU plug-in is available, KLU will be used by default. The KLU plug-in is provided with all WRspice distributions, and is installed in the startup directory.

nomatsort
Where set: Simulation Options/General

When using Sparse (i.e., KLU is unavailable or disabled), this boolean variable when set will prevent using element sorting to improve speed. This corresponds to the legacy WRspice sparse code. It may be interesting for comparison purposes, but setting this variable will slow simulation of most circuits. This variable has no effect if KLU is being used.

noopiter
Where set: Simulation Options/Convergence

This boolean variable applies when one of gminsteps or srcsteps is given a positive value, and thus operating point analysis (see 2.7.6) is using a Berkeley algorithm. In this case, by default a direct iterative solution of the circuit matrix is attempted, and if this fails the stepping methods are attempted. This initial direct solution attempt most often fails with complex circuits and can be time consuming. Setting noopiter> will skip this initial attempt.

noshellopts
This option is deprecated, use optmerge instead. See the section describing options (2.4.4.1) for a discussion of option merging and the role of this variable.

If set, do not use WRspice options that have been set interactively through the shell. Use only options that appear in a .options line in the circuit file when running a simulation of the circuit.

oldlimit
Where set: Simulation Options/Devices

When set, the SPICE2 limiting algorithm for MOS devices is used. Otherwise, an improved limiting procedure is used.

oldsteplim
In transient analysis, WRspice by default limits the maximum internal time step to the printing time step (tstep). This is obtained from the tran line

(simplified syntax)
.tran tstep tstop [tstart [tmax]]

I.e., tmax now defaults to tstep. Previously if defaulted to (tstop - tstart)/50, which is usually a much larger value.

The oldsteplim boolean option if given will revert the run to the earlier limiting condition.

It is important to understand the consequences of this difference. This change was made to improve results from circuits containing only devices that weakly limit the time step (e.g. MOSFETs, ring oscillator results) which otherwise can be ugly and wrong. This allows users of such devices to get good results without having to set an explicit maximum time step in the tran line.

However, if the printing time increment tstep is too small, the simulation time can dramatically increase, since these points are actually being calculated and not just interpolated. The user in this situation has several options:

1. Accept the longer analysis time as the cost of greater accuracy.
2. Use a larger printing time increment (tstep).
3. Use the tmax parameter to set a larger limit.
4. Use .options oldsteplim to use the old limit of (tstop - tstart)/50.

renumber
Where set: Simulation Options/Parser

When set, the source lines are renumbered sequentially after subcircuit expansion.

savecurrent
Where set: Simulation Options/General

If this variable is set, then all device current special vectors are saved in the plot by default during analysis. This enables plotting of device currents using the @device[param] construct.

spice3
Where set: Simulation Options/Timestep

By default, WRspice uses a custom algorithm for controlling integration order during transient analysis. This algorithm provides the following advantages over the SPICE3 algorithm:

1. It provides a possibly better determination of when to use higher integration orders. This is slightly different from the SPICE3 algorithm even for the order 2 that SPICE3 supports, and probably takes a few more Euler time steps, but the WRspice code appears to be less susceptible to trapezoid integration nonconvergence.

2. WRspice allows the full range of Gear integration orders, unlike SPICE3 which does not advance integration order above 2, when maxord is larger than 2. It is not clear how useful higher-order Gear integration is. Unlike Gear 2, which is much more stable in general than trapezoidal integration for stiff systems, this is not true of the higher orders.

3. When the time step is reduced and integration order is cut due to non-convergence, backward-Euler is now enforced for the next two time steps. In SPICE3, only the first time step is forced to be backward-Euler. The new approach reduces the tendency of some circuits to not converge when trapezoidal integration is used.

The standard SPICE3 logic can be used if desired, by setting the boolean option variable spice3. WRspice releases prior to 3.2.13 used the SPICE3 algorithm exclusively.

translate
This should be ignored. It enables some unneeded processing when building the circuit matrix internally.

trapcheck
Where set: Simulation Options/Timestep

In some circuits, whose equations are ``stiff'' in a mathematical sense, trapezoidal integration may not converge in transient analysis. These circuits likely have a low impedance (voltage source) driving a capacitor, and/or a high impedance driving an inductor. Non-convergence can take several forms:

1. The run exits with a ``timestep too small'' message.
2. The run exits with a math error such as overflow or underflow.
3. Circuit variables oscillate between values at every internal time point. The oscillations may increase in amplitude as simulation progresses.
4. Circuit variables monotonically diverge to huge values.

When using trapezoidal integration, there is a test to check for the oscillatory behavior characteristic of this type of nonconvergence. If nonconvergence is detected, the present time point is rejected, the time step is cut by a factor of eight, and the time point calculation is repeated using backward Euler integration. The circuit will return to trapezoid integration in a few internal time steps.

This is an improvement, but does not solve all convergence problems. In particular, this test will not detect monotonic divergence, which could be detected by other means but too late to do anything about it.

This test is not enabled by default, since it tends to cause circuits to simulate a little more slowly. It tends to produce false-positives which increase the iteration count. When needed, it can be enabled by setting the trapcheck variable.

In WRspice releases prior to 4.1.22, this test was enabled by default, and could be disabled by setting a variable named ``notrapcheck''. The notrapcheck variable is no longer recognized.

trytocompact
Where set: Simulation Options/Devices

This boolean variable is applicable only to the LTRA model. When specified, the simulator tries to condense LTRA transmission line past history of input voltages and currents.

useadjoint
Where set: Simulation Options/Devices

Most of the BSIM device models in WRspice have added code that builds an adjoint matrix which is used to accurately compute device currents. The computed currents are not used in the device models, but are available as simulation outputs. This has a small performance overhead so is not enabled by default, but will be enabled by setting this variable. Without this it may not be possible to obtain device currents during the simulation, using the device[param] ``pseudo-vector''.

In WRspice releases prior to 4.1.23, this feature was enabled by default, and a variable named ``noadjoint'' could be set to disable the feature. The noadjoint option is no longer recognized.

vasilent

When set, text generated from Verilog-A models is suppressed while simulating. This can be used to prevent debugging or other messages from appearing on the screen.