The Capacitance Extraction Interface

The interface uses an external program to extract capacitance values between conducting features in the layout. The interface supports the following capacitance extraction programs:

1. The FasterCap program from FastFieldSolvers.com. This commercial program is recommended for users with capacitance extraction as an important workflow element. The auto-refinement capability provides the best accuracy with the least amount of setup.

2. The FastCap program from Whiteley Research. The interface also provides a crude, linear panel refinement capability which can be used with this free version of FastCap, which is available from the Whiteley Research free software archive. We will refer to the Whiteley Research program as FastCap-WR to distinguish it from the MIT original.

The interface generates a unified list file, which is compatible with the programs listed above. It is not directly compatible with the original MIT FastCap program, or its derivatives, that require multiple input files. There are accessory programs lstpack and lstunpack available which convert between the formats, so the MIT FastCap can be used in a two-step flow involving unpacking.

This is the second generation capacitance extraction interface. The original capacitance extraction interface, found in releases 4.0.8 and earlier, was quite a bit more complicated. The present interface affords at least the following simplifications:

• The interface presently takes material from the current cell as input, there is no need to select and save things into the interface.

• There is no ``dataset name'', the file names use the current cell name as a base name.

• The output file is always a unified list file, there is no ``old format'' support except via the separate lstpack and lstunpack utilities.

• There is no graphical ``partition editor'' as FasterCap does not need external refinement.

The new interface, however, is much more flexible and powerful than the original interface.

• There is no longer a fixed assumption that layers are planar, or that layer ordering must begin with a conductor and alternate with insulators. Layers can appear in any order, and any layer can be planarizing, or not. If a layer is planarizing, it will have variable thickness such that the top surface is in one plane.

• There is a new layer-sequencing engine (see 12.8) that is also used by the Cross Section display command (in the View Menu), as well as for inductance/resistance extraction. Thus, the cross section display will always faithfully represent the assumptions used in the interface. Layer ordering is basically that shown in the layer table, though Via layers are allowed to be out of sequence (likely for drawing visibility reasons). The ``real'' position of a Via layer can be obtained from the layers it references.

• Geometry is taken from the current cell, to all levels of the hierarchy. There is provision for use of a special masking layer. If this layer is found in the layout, geometry will be clipped to the patterning on this layer.

• The substrate is now more accurately included in the calculation, taking into account the actual thickness and lateral extent.