This is a syntax extension to Verilog-A supported by ADMS. It allows additional information in parameter and variable declarations to be passed to the simulator.
parameter real c10 = 2e-30 from [0:1] (* info="GICCR constant" unit="A^2s" *);
real outTheta (* info="Theta" *);
The attributes are delimited by (* ... *) just ahead of the line-terminating semicolon. The content consists of keyword=value terms, separated by white space. The value is taken as a literal string, and should be double-quoted if it contains white space. The keyword can be any token, but only certain keywords are recognized by ADMS.
Models may use the following code to hide this construct from non-ADMS parsers.
`define ATTR(txt) (*txt*)
parameter real c10 = 2e-30 from [0:1] `ATTR(info="GICCR constant" unit="A^2s");
real outTheta `ATTR( info="Theta" );