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WRspice Input Format

Subsections

Input Format
Variable Expansion in Input
Title, Comments, Job Separation, and Inclusions
Initialization
Parameters and Expressions
Subcircuits
Analysis Specification
Output Generation
Parameter Measurement and Testing
- .measure Line
- .stop Line
Control Script Execution
- .exec, .control, .postrun, and .endc Lines
- .check, .checkall, .monte, and .noexec Lines
Verilog Interface
- .verilog, .endv Lines
- .adc Line
Circuit Elements
Device Models
- Default Models
- Analysis at Different Temperatures
Passive Element Lines
Voltage and Current Sources
Semiconductor Devices
Superconductor Devices
- Josephson Junctions
  - Josephson Junction Description
  - Josephson Junction (Tunnel Junction Model)
- Josephson Junction Model

Stephen R. Whiteley 2024-10-26